Advances in semiconductor manufacturing technologies have resulted in dramatically increased circuit packing densities and higher speeds of operation. In order to achieve such increased densities, a wide variety of evolutionary changes have taken place with respect to semiconductor processing techniques and semiconductor device structures over the years.
Many of these process and structural changes have been introduced in connection with device scaling, in which ever smaller device geometries have been achieved.
One consequence of conventional FET device scaling is a requirement to reduce operating voltages. The reduced operating voltages are required, at least in part, because conventional FET device scaling needs a thinner gate dielectric layer in order to produce the desired electrical characteristics in the scaled-down transistor. Without a reduction in operating voltage, the electric field impressed across the thinner gate dielectric during circuit operation can be high enough for dielectric breakdown to become a problem. In other words, scaled-down FETs may operate faster but they require operation at lower voltages.
It has been recognized that many integrated circuit designs require both low operating voltage FETs for their ability to operate at high speeds, and high operating voltage FETs for their ability to interface with high voltage signals provided by other electronic components. In response to this need manufacturers have developed and provided semiconductor manufacturing processes that offer two types of transistors for use within a single integrated circuit. These two types of transistors include a first type with low operating voltage and high speed, and a second type with a higher operating voltage and a lower speed.
Unfortunately, these semiconductor manufacturing processes do not provide FETs with the electrical characteristics of high speed and high operating voltage combined in a single device.
What is needed are semiconductor structures suitable for use as FETs in radio frequency (RF) applications with high operating voltages and high transistor fT.
It is noted that the cross-sectional representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures and process steps which they are illustrating.